1. Field of the Invention
The present invention relates to a memory control unit responsive to an input data packet input from a data-driven type processor for accessing image memory to output the result therefrom. More particularly, the present invention relates to a memory control unit responsive to an input data packet output from a dynamic data-driven type processor and having a generation number allotted in order of input time for accessing the content of image memory or the like to output the result therefrom, using that generation number as an address.
2. Description of the Background Art
In recent years, there is a growing demand for improving an operation speed of a processor, for example, in the field of image processing or the like. Parallel processing is regarded as promising as one of solutions for such a faster processor. An architecture called a data-driven type has especially drawn attention among other architectures for parallel processing.
In the data-driven type processor, a process proceeds in accordance with a simple rule that “a process is performed once all sets of input data necessary for a certain process are collected and resources such as an arithmetic unit necessary for that process are allocated”. A technique necessary for realizing this architecture includes a mechanism for detecting that all sets of input data are collected (firing). A system permitting only one set of input data for a process at the time of detecting the firing is referred to as a static data-driven type system and one permitting more than one sets of input data is referred to as a dynamic data-driven type system.
When time sequential data is processed, such as an image signal processing, the static data-driven type system cannot support the processing sufficiently and therefore it may be necessary to employ the dynamic architecture. In this case, since there are a plurality of input sets for a certain process, it is necessary to introduce a concept such as a generation identifier for identifying these plurality of input sets. In the following description, the generation identifier will be referred to as a generation number.
An exemplary data-driven type information processing apparatus for image processing as described above is shown in “An Evaluation of Parallel-Processing in the Dynamic Data-Driven Processor” (Information Processing Society of Japan, Microcomputer Architecture Symposium, Nov. 12, 1991).
Referring to FIG. 1, a system configuration of a data-driven type information processing apparatus will be described. As shown in FIG. 1, this system includes a data-driven type information processing apparatus 1000 and an image memory unit 1100. Image memory unit 1100 includes an image memory 1200 and a memory interface 1300. Data-driven type information processing apparatus 1000 has input ports 1002, 1004 respectively connected to data transmission paths 1006, 1008, output ports 1012, 1014 respectively connected to data transmission paths 1016, 1018, an output port 1022 connected to data transmission path 1026 to memory interface 1300, and an input port 1024 connected to data transmission path 1028 to memory interface 1300.
An input data packet having a generation number as an identifier that is attached in order of input time is time sequentially input through input ports 1002, 1004 to data-driven type information processing apparatus 1000. Data-driven type information processing apparatus 1000 stores a predetermined process, and a process is executed based on the stored content.
Memory interface 1300 receives through data transmission path 1026 an access request to image memory 1200 (a request for reference, updating or the like of data stored in the image memory) that is output from output port 1022 of data-driven type information processing apparatus 1000. Memory interface 1300 accesses image memory 1200 through a memory access control line and sends the result therefrom to input port 1024 of data-driven type information processing apparatus 1000 through data transmission path 1028.
Data-driven type information processing apparatus 1000 outputs an output data packet to data transmission paths 1016, 1018 through output ports 1012, 1014 after the processing for the input data packet is completed.
Referring to FIG. 2, an internal configuration of data-driven type information processing apparatus 1000 will be described. As shown in FIG. 2, data-driven type information processing apparatus 1000 includes a junction unit 1500, a firing control unit 1502 connected to junction unit 1500, a memory control unit 1504 connected to firing control unit 1502, an arithmetic unit connected to memory control unit 1504, a program storing unit 1508 connected to arithmetic unit 1506, and a branching unit 1510 connected to program storing unit 1508. Branching unit 1510 is also connected to junction unit 1500.
The input data packet input to input ports 1002, 1004 connected to data transmission paths 1006, 1008 is stored in firing control unit 1502 through junction unit 1500. Firing control unit 1502 has memory for queuing and queues the input data packet previously input in that memory until a data packet paired with the input data packet is input. Firing control unit 1502 passes the paired input data packets to memory control unit 1504 when these input data packets are collected. Memory control unit 1504 executes an access request to internal memory or image memory 1200 based on tag information or data included in the input data packet to reference or update the data stored in the memory. Arithmetic unit 1506 selects a processing in accordance with an instruction code included in the input data packet and executes an operation corresponding to the selected processing. The resultant operation is sent to program storing unit 1508. Program storing unit 1508 includes program memory storing an instruction code to be executed next and a node number. This node number is used as an address to execute an access to the program memory.
FIG. 3 shows a packet configuration of an input data packet. The input data packet includes an instruction code, a node number, a generation number, a right and left attribute flag, data (first data, second data, . . . ) in order from the upper bit. The instruction code is a code for specifying a stored instruction in order to read and execute the instruction stored in an instruction decoder. The node number is used as an address for referring to the instruction code stored in the program memory included in program storing unit 1508 with the node number. The generation number is used as an identifier for identifying the input data packet. It is noted that the generation number can also be used as an image address, and in this case, the generation number indicates a field number, a line number, and a pixel number in order from the upper bit.
In this system, when the internal memory functions as a look up table, the data stored in a data region or a generation number region has been used as address. When the internal memory is shared between a plurality of programs, a region is reserved for example in a portion of an instruction code in advance and the data stored in that region is attached as an identifier to the high order in the address as a page address. In this way, a usable range in the memory is determined based on a predetermined address for each program.
FIG. 4 shows a packet configuration of the data packet after firing, including a generation number (GE#), data (DATA (0)), and a constant (CST) in their respective storing regions. It is noted that in the data packet shown in FIG. 4, for the sake of clarity, the instruction code region, the node number region and data other than DATA (0) are not shown. As shown in FIG. 4, the lower bits (in this case 16 bits) of the address signal necessary for access to the memory is retrieved from the generation number region by masking the generation number (GE#) (MASKED ADDRESS). The page address (PA) stored in the lower three bits in the constant region is attached to the high order in MASKED ADDRESS as a page address to generate a 19-bit address signal for accessing the memory. In other words, a 16-bit generation number serves as the address for the memory and the lower three bits in the constant region are attached to the high order in that address as a page address, resulting in a 19-bit address signal.
In generating the address signal in this way, the page address has to be variable in order to utilize the memory region effectively by changing the number of pages or by changing the memory region divided by the pages. In this case, an operation is performed on the generation number, and based on the result of the operation, the memory is accessed.
FIG. 5 shows a flowchart of conversion to a 4-bit page address by increasing the page address by one bit, for the generation number of the input data packet as being input.
At step (abbreviated as S hereinafter) 1000, an input data packet is input through data transmission paths 1006, 1008. The input data packet as being input has a packet configuration as shown in FIG. 4. At S1002, AND operation of the generation number (GE#) and a first constant is executed. In this AND operation, the generation number (GE#) is ANDed with the first constant (0×7ff, 0111111111111111). Therefore, the generation number is rewritten, and the sixteenth bit (the most significant one bit) of the 16-bit generation number (GE#) masked and extracted is forced to be “0” for available for later use as a page address.
At S1004, an OR operation of the rewritten generation number and a second constant is executed. Here it is assumed that the sixteenth bit is converted to “1”. The OR operation is executed in which the generation number (GE#) is ORed with the second constant (0×8000, 1000000000000000). Therefore, the generation number is rewritten and the sixteenth bit of the generation number is “1”.
At S1006, TSEL instruction is executed. In this TSEL instruction, based on the 19-bit address signal having a third constant (a page address represented by the lower three bits in the constant region shown in FIG. 4) attached to the high order in the rewritten generation number, the internal memory is accessed and the data stored in the memory is referenced.
As shown in FIG. 6, such processing enables the internal memory to be accessed with an address formed of the first to fifteenth bits in the generation number region and a page address formed of the sixteenth bit of the generation number (GE#) included in the input data packet and the lower three bits in the constant region. In this way, a 3-bit page address is converted to four bits.
A fixed page address, however, cannot optimize the use of memory if the capacity of the memory for use in each process varies where a plurality of processes are combined in one application. For example, if the page address is 3-bit, the memory can be used only in eight ways regardless of the memory capacity for use when the memory is used in an application. Furthermore, as described above, for example conversion of three bits to four bits requires the process constituted with three instructions, resulting in the reduced processing speed.